apex microtechnology corporation telephone (520) 690-8600 fax (520) 888-3329 orders (520) 690-8601 email prodlit@apexmi crotech.com features monolithic mos technology low cost high voltage operation?350v, 250v derate low quiescent current?2ma no second breakdown high output current?120 ma peak applications telephone ring generator pie zo electric positioning electrostatic transducer & deflection deformable mirror focusing packaging options 7to-220 plastic package (PA140cd) 7to-220 with staggered lead form (PA140cx) 7 ddpak surface mount package (PA140cc) description the PA140 is a high voltage monolithic mosfet operational ampli er achieving performance features previously found only in hybrid designs while increasing reliability. inputs are protected from excessive common mode and differential mode voltages. the safe operating area (soa) has no second breakdown limitations. external compensation provides the user exibility in choosing optimum gain and bandwidth for the application. the PA140 is packaged in three standard package designs. the surface mount version of the PA140, the PA140cc, is an industry standard non-hermetic plastic 7-pin ddpak. the through hole versions of the PA140, the PA140cd, and the PA140cx, are industry standard non-hermetic plastic 7-pin to-220 packages. the PA140cx is a staggered lead formed PA140cd and offers industry standard 100 mil spacing, this allows for easier pc board layout. (please reference to the lead form datasheet drawing lf005 for package dimensions of the PA140cx.) high voltage considerations should be taken when designing board layouts for the PA140. the PA140cd may require a derate in supply voltage depending on the spacing used for board layout. the 15-mil and 14-mil minimum spacing of the 7to-220 and 7ddpak respectively is adequate to standoff the 350v rating of the PA140. however, a supply voltage derate to 250v is required if the spacing of circuit board artwork is less than 11 mils. in cases where the PA140 is used to it's maximum voltage rating, the PA140bp is recommended given that the staggered lead form allows for 100-mil standard spacing. the monolithic ampli er is directly attached to the metal tabs of the PA140cc, PA140cd, and PA140cx. the metal tabs are directly tied to -v s the PA140 is set for a gain of 38.5 boosting the 2.33v signal to 90v. the recommended compensation for gains above 30 is used. if capacitive loading is at least 330pf at all times, the recommended snubber network may be omitted. http://www.apexmicrotech.com (800) 546-apex (800) 546-2739 microtechnology high voltage power operational amplifier PA140 a1 PA140 a2 PA140 20r piezo transducer 20r rn 20r cn r v in 175 +175 175 +175 2.2k 10pf 10pf 330pf 330pf 100 ? 100 ? 2.2k low cost 660v p-p piezo drive typical applicaton ref application note 31 "basic op amp theory and practice" external connections PA140cc -in +in +vs -vs out comp (rc) comp (cc) -in +in+ +vs -vs out comp (rc) comp (cc) -in +in +vs -vs out comp(rc) comp(cc) PA140cd PA140cx phase compensation gain c c r c 1 18pf 2.2k 10 10pf 2.2k 30 3.3pf 2.2k c ,c are rated for full supply voltage. c is npo = 3 r cl i lim s c c
apex microtechnology corporation 5980 north shannon road tucson, arizona 85741 usa applications hotline: 1 (800) 546-2739 absolute maximum ratings specifications PA140 absolute maximum ratings supply voltage, +v s to v s 350v derated supply voltage +v s to -v s 250v output current, continuous within soa 60 ma output current, peak 120 ma power dissipation, continuous @ t c = 25 c 14w input voltage, differential 16 v input voltage, common mode v s temperature, pin solder 10 sec 220 c temperature, junction 2 150 c temperature, storage 65 to +150 c temperature range, powered (case) 40 to +125 c caution the PA140 is constructed from mosfet transistors. esd handling procedures must be observed. parameter test conditions 1 min typ max units input offset voltage, initial 15 30 mv offset voltage, vs. temperature 4 full temperature range 70 130 v/ c offset voltage, vs supply 20 32 v/v offset voltage, vs time 75 v kh bias current, initial 50 2 00 pa bias current, vs supply 2 20 pa/v offset current, initial 50 200 pa input impedance, dc 101 1 input capacitance 5 pf common mode, voltage range vs 12 v common mode rejection, dc vcm = 90v dc 84 94 db noise, broad band 10khz bw, rs = 1k 50 v rms noise, low frequency 1-10 hz 110 v p-p gain open loop at 15hz rl = 5k 94 106 db bandwidth, open loop 1.6 mhz power bandwidth cc = 10pf, 280v p-p 26 khz phase margin full temperature range 60 output voltage swing io = 40ma vs 12 vs 10 v current, peak 5 120 ma current, continuous 60 ma settling time to .1% cc = 10pf, 10v step, av = 10 12 s slew rate cc = open 40 v/s capacitive load av = +1 10 nf resistance6, n o load rcl = 0 150 resistance6, 20 m a load rcl = 0 25 power supply voltage 3 see note 3 50 150 175 v current, quiescent 1.6 2.0 ma thermal resist ance, ac junction to case 6 f > 6 0hz 5.9 6.85 c/w resist ance, dc junction to case 6 f < 6 0hz 7.7 8.9 c/w resistance, junction to air full temperature range c/w temperature range, case meets full range speci cations 25 25 +85 c specifications notes: 1. unless otherwise noted t c = 25 c, c c = 18pf, r c = 2.2k. dc input speci cations are value given. power supply voltage is typical rating. 2. long term operation at the maximum junction temperature will result in reduced product life. derate inter nal power dissipation to achieve high mttf. 3. derate maximum supply voltage .5 v/ c below case temperature of 25 c. no derating is needed above tc = 25 c. 4. sample tested by wafer to 95%. 5. guaranteed but not tested. PA140
apex microtechnology corporation telephone (520) 690-8600 fax (520) 888-3329 orders (520) 690-8601 email prodlit@apexmicrotech.com typical performance graphs PA140 1 100 10m frequency, f (hz) 20 0 60 120 small signal response open loop gain, a(db) 20 40 80 100 1 100 1k 1m frequency, f (hz) 0 80 120 common mode rejection common mode rejection, cmr (db) 20 60 100 100 10k frequency, f (hz) .002 harmonic distortion distortion, (%) .02 1.0 30k 200 1k 10 10k .1m 10 1k 10k .1m 1m 3k 100k .004 .04 40 c c = 18pf c c = 10pf c c = 3.3pf .006 .01 .06 .1 .2 .4 .6 v o = 180v pp v o = 60v pp v o = 30v pp a v = 20 c c = 3.3pf r l = 2k ? 0 25 50 75 100 125 temperature, tj ( c) 0 power derating internal power dissipation, p(w) 100 150 300 350 total supply voltage, v s (v) normalized quiescent current, (%) 1 100 .1m 10m 210 150 60 0 phase response 90 30 10k 20k .2m .1m frequency, f (hz) 20 output voltage, v (v ) o 11m frequency, f (hz) 0 20 120 power supply rejection power supply rejection, psr (db) 40 100 04060 output current, i o (ma) 2 10 output voltage swing voltage drop from supply, v s v o (v) 4 8 0 compensation capacitance, c c (pf) slew rate slew rate, v/ s 20 120 0 quiescent current 200 50 70 90 1k power response pp 30k 10 100 1k 10k .1m 80 0 10 10k 1m frequency, f (hz) phase, ( ) ? 420 816 12 10 20 30 40 50 60 40 60 80 100 200 400 80 60 180 120 110 130 150 6 c c = 18pf c c = 18pf c c = 10pf c c = 3.3pf c c = 3.3pf c c = 10pf 50k .3m .5m 1m c c = 10pf c c = 3.3pf c c = 18pf r l = 10k ? 250 t c = -25 c t c = 2 5 c t c = 85 c 12 100 +v s v s 25 c out 25 c +out 85 c out 25 c ou t 85 c +out 25 c +out 14 16 18 4 8 6 2 10 12 14 16
apex microtechnology corporation 5980 north shannon road tucson, arizona 85741 usa applications hotline: 1 (800) 546-2739 operating considerations PA140 general please read application note 1 "general operating considerations" which covers stability, supplies, heat sinking, mounting, current limit, soa interpretation, and speci cation interpretation. visit www.apexmicrotech.com for design tools that help automate tasks. input protection the PA140 inputs are protected against common mode voltages up the supply rails and differential voltages up to 16 volts as well as static discharge. differential voltages exceeding 16 volts will be clipped by the protection circuitry. however, if more than a few milliamps of current is available from the overload source, the protection circuitry could be destroyed. the protection circuitry includes 300 ohm current limiting resistors at each input, but this may be insuf cient for severe overloads. it may be necessary to add external resistors to the application circuit where severe overload conditions are expected. limiting input current to 1ma will prevent damage. stability the PA140 has suf cient phase margin when compensated for unity gain to be stable with capacitive loads of at least 10 nf. however, the low pass circuit created by the sumpoint ( in) capacitance and the feedback network may add phase shift and cause instabilities. as a general rule, the sumpoint load resistance (input and feedback resistors in parallel) should be 1k ohm or less at low gain settings (up to 10). alternatively, use a bypass capacitor across the feedback resistor. the time constant of the feedback resistor and bypass capacitor combination should match the time constant of the sumpoint resistance and sumpoint capacitance. the PA140 is externally compensated and performance can be tailored to the application. use the graphs of small signal gain and phase response as well as the graphs for slew rate and power response as a guide. the compensation capacitor c c must be rated at 350v. the compensation capacitor and associated resistor r c must be mounted closely to the ampli er pins to avoid spurious oscillation. an npo capacitor is recommended for compensation. the PA140 monolithic ampli er uses an all nmos output topology that presents a special stability problem. an output snubber network of 330pf and 100 ? in series from the output to v s will eliminate this problem. this network is not required if the load capacitance is greater than 330pf. mounting the PA140cc 7-pin ddpak surface mountable package has a large exposed integrated copper heatslug to which the monolithic ampli er is directly attached. the PA140cc requires surface mount techniques of heatsinking. a solder connection to an area of 1 to 2 square inches of foil is recommended for circuit board layouts. this may be adequate heatsinking but the large number of variables involved suggests temperature measurements to be made on the top of the package. surface mount techniques include the use of a surface mount fan in combination with a surface mount this data sheet has been carefully checked and is believed to be reliable, however, no responsibility is assumed for possible i naccuracies or omissions. all speci cations are subject to change without notice. PA140u rev. a february 2002 ? 2002 apex microtechnology corp. 10 20 30 50 100 200 300 500 output current from +v s or v s , (ma) 2 3 4 5 10 20 30 40 50 100 PA140 soa 200ms 120 200 dc, t c = 85 c 300ms dc , t c = 25 c heatsink on the backside of the fr4/pc board, or copper slug. do not allow the temperature to exceed 85 c. the heatslug is tied internally to -v s . safe operating area (soa) the mosfet output stage of this power operational ampli er has two distinct limitations: 1. the current handling capability of the die metallization. 2. the temperature of the output mosfets. note: the output stage is protected against transient yback. however, for protection against sustained, high energy yback, external fast-recovery diodes should be used. equivalent schematic in +v s v s +in d2 d3 d4 d5 q5 q4 1 2 4 5 3 q1 q11 q12 d1 q2 q6 q8 q13 sub q14 q10 q3 i out comp comp 6 7 application references: for additional technical information please refer to the following application notes: an 01: general operating considerations an 25: driving capacitive loads an 38: loop stability with reactive loads
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